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Design Through Verilog HDL (Record no. 57522)
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| 000 -LEADER | |
|---|---|
| fixed length control field | 00592nam a2200217Ia 4500 |
| 003 - CONTROL NUMBER IDENTIFIER | |
| control field | AVIT |
| 005 - DATE AND TIME OF LATEST TRANSACTION | |
| control field | 20211120080812.0 |
| 008 - FIXED-LENGTH DATA ELEMENTS--GENERAL INFORMATION | |
| fixed length control field | 080821s2004 ||||||||||||||||| ||und|d |
| 020 ## - INTERNATIONAL STANDARD BOOK NUMBER | |
| Printed Price | INR 248.00 |
| 100 ## - FIRST AUTHOR (IF A PERSON) | |
| Name of author | Padmanabhan T,r |
| 115.187.37.79 | Author |
| 245 #0 - TITLE STATEMENT | |
| Title | Design Through Verilog HDL |
| Statement of responsibility | Padmanabhan T,r; B. Bala Tripura Sundari |
| 250 ## - EDITION STATEMENT | |
| Edition statement | 2004 |
| 260 ## - PUBLICATION, DISTRIBUTION, ETC. | |
| Name of publisher | John Wiley & Sons |
| Date of publication, distribution, etc. | 2004 |
| 650 ## - SUBJECT ADDED ENTRY--TOPICAL TERM | |
| Subject heading | Electronics |
| 700 ## - ADDITIONAL AUTHOR (INDIVIDUAL) | |
| Author name | B. Bala Tripura Sundari |
| Relator term | Author |
| 942 ## - ADDED ENTRY ELEMENTS (KOHA) | |
| Source of classification or shelving scheme | |
| Koha item type | Books |
| 653 ## - INDEX TERM--UNCONTROLLED | |
| -- | verilog hdl |
| Withdrawn status | Lost status | Source of classification or shelving scheme | Damaged status | Not for loan (e.g. reference copy) | Home library | Current library | Date acquired | Source of acquisition | Purchase price (after disc. etc) | Total Checkouts | Accession No | Date last seen | Price effective from | Koha item type |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| AVIT Central Library | AVIT Central Library | 21/08/2008 | Bs@ds | 248.00 | 16271 | 20/11/2021 | 20/11/2021 | Books | ||||||
| AVIT Central Library | AVIT Central Library | 21/08/2008 | Bs@ds | 248.00 | 16272 | 20/11/2021 | 20/11/2021 | Books |